1. Technical Field
The present invention relates to parallel programming techniques and, in particular, to systems and methods which employ a parallel programming model that does not require coherence.
2. Description of the Related Art
Modern computer systems require fast caches to enable processors to exploit their computational capabilities without being hampered excessively by the comparatively slow access to main memory. Thus multiple pieces of physical memory (e.g., in caches of several cores and one main memory location) may be simultaneously associated with a single location X in virtual memory. This creates multiple physical views of one location in the shared virtual address space.
Due to the existence of multiple physical views of one virtual address space, location mechanisms are required to ensure that these different views result in the same outcome when determining the memory's content. In hardware that supports multi-threading with mutices, this is achieved via cache-coherence by disallowing correct programs from ‘seeing’ differing views.